可享批量折扣
小计 17 件 (按托盘提供)*
¥1,971.32
(不含税)
¥2,227.51
(含税)
有库存
- 155 件将从其他地点发货
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单位 | 每单位 |
|---|---|
| 17 - 32 | RMB115.96 |
| 33 + | RMB113.65 |
* 参考价格
- RS 库存编号:
- 177-3830P
- 制造商零件编号:
- KSZ8895FQXIA
- 制造商:
- Microchip
产品技术参数
产品技术参数资料
法例与合规
产品详细信息
通过选择一个或多个属性来查找类似产品。
选择全部 | 属性 | 值 |
|---|---|---|
| 品牌 | Microchip | |
| 芯片类型 | 开关芯片 | |
| 数据速率 | 10/100Mbps | |
| 光纤支持 | 是 | |
| 端口数目 | 5 | |
| 安装类型 | 贴片 | |
| VLAN支持 | 是 | |
| 封装类型 | PQFP | |
| 引脚数目 | 128 | |
| 典型工作电源电压 | 3.3 V | |
| 尺寸 | 2.9 x 20 x 14mm | |
| 最高工作温度 | +85 °C | |
| 最低工作温度 | -40 °C | |
| 选择全部 | ||
|---|---|---|
品牌 Microchip | ||
芯片类型 开关芯片 | ||
数据速率 10/100Mbps | ||
光纤支持 是 | ||
端口数目 5 | ||
安装类型 贴片 | ||
VLAN支持 是 | ||
封装类型 PQFP | ||
引脚数目 128 | ||
典型工作电源电压 3.3 V | ||
尺寸 2.9 x 20 x 14mm | ||
最高工作温度 +85 °C | ||
最低工作温度 -40 °C | ||
- COO (Country of Origin):
- TW
The KSZ8895MQX/RQX/FQX/ML is a highly-integrated, Layer 2 managed, five-port switch with numerous features designed to reduce system cost.
Advanced Switch Features
VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs)
Static MAC table supports up to 32 entries
VLAN ID tag/untag options, per port basis
Comprehensive Configuration Register Access
Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers
High-speed SPI (up to 25MHz) and I2C master Interface to all internal registers
I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode
QoS/CoS Packet Prioritization Support
Per port, 802.1p and DiffServ-based
1/2/4-queue QoS prioritization selection
Programmable weighted fair queuing for ratio control
Integrated 5-Port 10/100 Ethernet Switch
New generation switch with five MACs and five PHYs
PHYs designed with patented enhanced mixed-signal technology
VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs)
Static MAC table supports up to 32 entries
VLAN ID tag/untag options, per port basis
Comprehensive Configuration Register Access
Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers
High-speed SPI (up to 25MHz) and I2C master Interface to all internal registers
I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode
QoS/CoS Packet Prioritization Support
Per port, 802.1p and DiffServ-based
1/2/4-queue QoS prioritization selection
Programmable weighted fair queuing for ratio control
Integrated 5-Port 10/100 Ethernet Switch
New generation switch with five MACs and five PHYs
PHYs designed with patented enhanced mixed-signal technology