Microchip Technology PIC24F单片机, PIC内核, 44针, TQFP, 最大32MHz, 16 kB 闪存, 2 kB RAM
- RS 库存编号:
- 177-3577
- 制造商零件编号:
- PIC24F16KM204-I/PT
- 制造商:
- Microchip Technology
不可供应
RS 不再对该产品备货。
- RS 库存编号:
- 177-3577
- 制造商零件编号:
- PIC24F16KM204-I/PT
- 制造商:
- Microchip Technology
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选择全部 | 属性 | 值 |
|---|---|---|
| 品牌 | Microchip Technology | |
| 系列名称 | PIC24F | |
| 封装类型 | TQFP | |
| 安装类型 | 贴片 | |
| 引脚数目 | 44 | |
| 装置核芯 | PIC | |
| 数据总线宽度 | 16Bit | |
| 程序存储器大小 | 16 kB | |
| 最大频率 | 32MHz | |
| 内存大小 | 2 kB | |
| PWM单元数目 | 1 | |
| SPI通道数目 | 2 | |
| UART通道数目 | 2 | |
| 典型工作电源电压 | 3.6 V（最大） | |
| I2C通道数目 | 2 | |
| 尺寸 | 10 x 10 x 1.05mm | |
| 脉冲宽度调制 | 1（3 x 16 位） | |
| 最高工作温度 | +85 °C | |
| 模数转换器单元数目 | 1 | |
| 长度 | 10mm | |
| 模数转换器 | 1（22 x 12 位） | |
| 最低工作温度 | -40 °C | |
| 程序存储器类型 | 闪存 | |
| 宽度 | 10mm | |
| 高度 | 1.05mm | |
| 选择全部 | ||
|---|---|---|
品牌 Microchip Technology | ||
系列名称 PIC24F | ||
封装类型 TQFP | ||
安装类型 贴片 | ||
引脚数目 44 | ||
装置核芯 PIC | ||
数据总线宽度 16Bit | ||
程序存储器大小 16 kB | ||
最大频率 32MHz | ||
内存大小 2 kB | ||
PWM单元数目 1 | ||
SPI通道数目 2 | ||
UART通道数目 2 | ||
典型工作电源电压 3.6 V（最大） | ||
I2C通道数目 2 | ||
尺寸 10 x 10 x 1.05mm | ||
脉冲宽度调制 1（3 x 16 位） | ||
最高工作温度 +85 °C | ||
模数转换器单元数目 1 | ||
长度 10mm | ||
模数转换器 1（22 x 12 位） | ||
最低工作温度 -40 °C | ||
程序存储器类型 闪存 | ||
宽度 10mm | ||
高度 1.05mm | ||
- COO (Country of Origin):
- US
The eXtreme low power, PIC24F MCU includes up to 1MB of Flash memory with Error Correction Code ( ECC) and 32 KB of RAM.
CPU:
Modified Harvard Architecture
Up to 16 MIPS Operation @ 32MHz
8MHz Internal Oscillator:
96MHz PLL option
Multiple clock divide options
Run-time self-calibration capability for maintaining better than ±0.20% accuracy
Fast start-up
17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
32-Bit by 16-Bit Hardware Divider
16 x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Live Update:
Dual Partition Flash with Live Update Capability
Capable of Holding Two Independent Software Applications, including Bootloader
Permits Simultaneous Programming of One Partition while Executing Application Code from the Other
Allows Run-Time Switching Between Active Partitions
Modified Harvard Architecture
Up to 16 MIPS Operation @ 32MHz
8MHz Internal Oscillator:
96MHz PLL option
Multiple clock divide options
Run-time self-calibration capability for maintaining better than ±0.20% accuracy
Fast start-up
17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
32-Bit by 16-Bit Hardware Divider
16 x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Live Update:
Dual Partition Flash with Live Update Capability
Capable of Holding Two Independent Software Applications, including Bootloader
Permits Simultaneous Programming of One Partition while Executing Application Code from the Other
Allows Run-Time Switching Between Active Partitions