Microchip PHY芯片, 1000Mbit/s以太网收发器, QFN封装, 支持1000BASE-T，100BASE-TX，10BASE-T，IEEE 802.3标准, 48引脚, 7 x 7 x 0.8mm

The KSZ9031 reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.

Single-chip 10/100/1000Mbps Ethernet transceiver
KSZ9031Mxx feature GMII/MII standard interface with 3.3V/2.5V/1.8V tolerant I/Os
KSZ9031Rxx feature RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options for external delay and making adjustments and corrections to TX and RX timing paths
GMII/MII/RGMII with 3.3V/2.5V/1.8V tolerant I/Os
Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full)
On-chip termination resistors for the differential pairs
On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core
Jumbo frame support up to 16KB
125MHz Reference Clock Output
Energy-detect power-down mode